The present invention relates generally to integrated circuit designs, and more particularly to a two-port static random access memory (SRAM) device with a high speed sensing scheme.
Static Random access memory (SRAM) is typically used for temporary storage of data in a computer system. SRAM retains its memory state without the need of any data refresh operations as long as it is supplied with power. A SRAM device is comprised of an array of “cells,” each of which retains one “bit” of data. A typical SRAM cell may include two cross coupled inverters and two access transistors connecting the inverters to complementary bit-lines. The two access transistors are controlled by word-lines to select the cell for read or write operation. In read operation, the access transistors are switched on to allow the charges retained at storage nodes of the cross coupled inverters to be read via the bit line and its complement. In write operation, the access transistors are switched on and the voltage on the bit line or the complementary bit line is raised to a certain level to flip the memory state of the cell.
FIG. 1 schematically illustrates a typical six transistor SRAM cell 100. The SRAM cell 100 is comprised of PMOS transistors 102 and 104, and NMOS transistors 106, 108, 110 and 112. The PMOS transistor 102 has its source connected to a supply voltage Vcc, and its drain connected to a drain of the NMOS transistor 106. The PMOS transistor 104 has its source connected to the supply voltage Vcc, and its drain connected to a drain of the NMOS transistor 108. The sources of the NMOS transistors 106 and 108 are connected together to a complementary supply voltage, such as ground voltage or Vss. The gates of the PMOS transistor 102 and the NMOS transistor 106 are connected together to a storage node 114, which is further connected to the drains of the PMOS transistor 104 and the NMOS transistor 108. The gates of the PMOS transistor 104 and the NMOS transistor 108 are connected together to a storage node 116, which is further connected to the drains of the PMOS transistor 102 and the NMOS transistor 106. The NMOS transistor 110 connects the storage node 116 to a bit line BL, and the NMOS transistor 112 connects the storage node 114 to a complementary bit line BLB. The gates of the NMOS transistors 110 and 112 are controlled by a word line WL. When the voltage on the word line WL is a logic “1,” the NMOS transistors 110 and 112 are turned on to allow a bit of data to be read from or written into the storage nodes 114 and 116 via the bit line BL and the complementary bit line BLB.
One drawback of the typical six transistor SRAM cell 100 is that its operation speed and cell size are strictly limited due to reliability concerns. Moreover, it requires a relatively high supply voltage, which leads to high power consumption.
Conventionally, dual-port SRAM and two-port SRAM have been widely used for high speed applications, wherein a major difference between them is that a dual-port SRAM cell has one pair of bit lines and a complementary bit line for write operation and another pair of bit lines and a complementary bit line for read operation, whereas a two-port SRAM cell has one pair of bit line and complementary bit line for write operation, and only a single bit line for read operation. Although the dual-port SRAM has a faster operation speed, the two-port SRAM is smaller in size and lower in supply voltage. As such, it is desired to improve the operation speed of the two-port SRAM in order to provide a solution for SRAM in high speed and low power consumption applications, without area penalty.